Semiconductor electronic devices may be formed on silicon-on-insulator (SOI) substrates with reduced parasitic and nodal capacitances, increased radiation hardness and reduced process complexity compared to bulk semiconductor devices. In particular, electronic devices such as SOI field effect transistors (FETs) typically have lower source/drain-to-substrate capacitance and higher latch-up immunity compared to their bulk counterparts. However, floating body effects caused by the presence of a continuous insulating layer may limit performance of conventional SOI FETs. Lower source-drain breakdown voltage caused by parasitic bipolar action also limits performance of conventional SOI FETs.
Electronic devices such as bipolar junction transistors (BJTs) may also benefit from being formed in monocrystalline SOI substrates, particularly when the extrinsic base and extrinsic collector contact regions are monocrystalline as well. Presently, the most popular commercial high-speed BJT structure is the Super Self-Aligned Transistor (SST) of FIG. 1. This BJT is typically characterized by a relatively low emitter-base capacitance (C.sub.eb), but a relatively high base-collector capacitance (C.sub.bc). Double Self-Aligned Transistors (DSTs) such as the Sidewall Contacted Structure (SICOS) of FIG. 2 typically have lower C.sub.bc, however these devices employ a polycrystalline extrinsic base contact region. To compensate for this, the edges of the base-collector junction are moved away from the polycrystalline extrinsic base contact region to prevent the depletion region in the intrinsic base from contacting the extrinsic base contact region during operation. For example, an extrinsic-to-intrinsic base link-up region is typically used adjacent the intrinsic collector region to provide the necessary separation, as illustrated by FIG. 2. This results in an increase in the base-collector junction area and prevents even smaller C.sub.bc from being achieved with DST devices.
Electronic devices which include a combination of Complimentary Metal-Oxide-Semiconductor (CMOS) FETs and BJTs (e.g., BiCMOS) can also be expected to achieve higher performance characteristics when formed on SOI substrates, particularly when all the active regions of the devices are monocrystalline and floating body effects have been eliminated. Attempts have been made to form BiCMOS devices on SOI substrates. For example, U.S. Pat. No. 5,049,513 to Eklund discloses a method of fabricating a BJT and a FET transistor on an SOI substrate. U.S. Pat. No. 5,212,397 to See et al. and U.S. Pat. No. 5,258,318 to Buti et al. also disclose BiCMOS devices and methods of forming the same on SOI substrates.
Notwithstanding these attempts to incorporate BJT and FET electronic devices on SOI substrates, there still exists a need for improved electronic devices such as FETs, BJTs and BiCMOS devices on SOI substrates, and methods of forming same, which have monocrystalline active regions, lower parasitic capacitances and reduced susceptibility to floating body effects and parasitic latch-up.